1. Field of the Invention
The invention relates to an arrangement for the synchronous output of analog signals generated in two or more digital-to-analog converters.
2. Related Technology
Conventional digital-to-analog conversion generally uses two mutually-synchronous clock pulses. In this context, one clock pulse controls the digital component, while another clock pulse with special requirements regarding the purity of the clock pulse controls the actual converter. The signals are generally transferred between these clock pulses in a synchronous manner, that is to say, with a known delay. With fast clock-pulse rates, maintaining the corresponding set-up and hold times at the transfer interface becomes increasingly difficult, and accordingly, a fifo (first-in-first-out memory) is connected in series to the actual converter for the transfer of the signals. This fifo memory is generally integrated in the converter. This arrangement does in fact allow a synchronization with constant delay of the signal, dependent upon the initialization of the fifo memory; however, the delay can assume different values. Accordingly, the intermediate connection of a fifo memory has so far not completely resolved the problem at fast clock-pulse rates.
A special problem occurs, if analog signals generated in this manner must be generated synchronously relative to one another or synchronously relative to a marker signal, which is in fact generated together with the digital signal generating the analog signals, but not output via the digital-to-analog converter. In this case, the uncertain phase position of the analog signals relative to the marker signal is critical.